Electrode/dielectric barrier material formation and structures

ABSTRACT

Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.16/913,549, filed Jun. 26, 2020, the contents of which are incorporatedherein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices andmethods, and more particularly to forming a barrier material between anelectrode and a dielectric to reduce oxygen vacancies in the dielectricmaterial and to increase the breakdown voltage of the dielectric.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory, including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), staticrandom access memory (SRAM), synchronous dynamic random access memory(SDRAM), ferroelectric random access memory (FeRAM), magnetic randomaccess memory (MRAM), resistive random access memory (ReRAM), and flashmemory, among others. Some types of memory devices may be non-volatilememory (e.g., ReRAM) and may be used for a wide range of electronicapplications in need of high memory densities, high reliability, and lowpower consumption. Volatile memory cells (e.g., DRAM cells) requirepower to retain their stored data state (e.g., via a refresh process),as opposed to non-volatile memory cells (e.g., flash memory cells),which retain their stored state in the absence of power. However,various volatile memory cells, such as DRAM cells may be operated (e.g.,programmed, read, erased, etc.) faster than various non-volatile memorycells, such as flash memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example top-down view of a storage node includinga barrier material formed between a top electrode and a dielectricmaterial of the storage node in accordance with a number of embodimentsof the present disclosure.

FIG. 2 illustrates another barrier material placement in an exampletop-down view of a storage node including a barrier material formedbetween a bottom electrode and a dielectric material of the storage nodein accordance with a number of embodiments of the present disclosure.

FIG. 3 illustrates another barrier material placement in an exampletop-down view of a storage node including a barrier material formedbetween both a top electrode and a bottom electrode and a dielectricmaterial of the storage node in accordance with a number of embodimentsof the present disclosure.

FIG. 4A illustrates an example cross-sectional side view of the storagenode illustrated in FIG. 1 taken along cut line 4-4.

FIG. 4B illustrates an example cross-sectional side view of a storagenode including a barrier material formed as a “bi-layer” structurebetween a top electrode and a dielectric material of the storage node inaccordance with a number of embodiments of the present disclosure.

FIG. 5 is a flow diagram of an example method for forming a barriermaterial between a top electrode and a dielectric material of a storagenode in a semiconductor fabrication process in accordance with a numberof embodiments of the present disclosure.

FIG. 6 is a flow diagram of an example method for depositing a barriermaterial between a bottom electrode and a dielectric material of astorage node in a semiconductor fabrication process in accordance with anumber of embodiments of the present disclosure.

FIG. 7 is a flow diagram of an example method for forming a barriermaterial between both a bottom electrode and a dielectric material and atop electrode and the dielectric material in accordance with a number ofembodiments of the present disclosure.

FIG. 8 is a representation of a processing apparatus which may be used,at least in part, for implementation of an example semiconductorfabrication process in accordance with a number of embodiments of thepresent disclosure.

FIG. 9 illustrates a functional block diagram of a computing systemincluding at least one semiconductor structure such as a storage node ina memory array formed in accordance with a number of embodiments of thepresent disclosure.

DETAILED DESCRIPTION

Various types of memory devices, including arrays of volatile and/ornon-volatile memory cells (e.g., a memory array), may include thinelectrodes, e.g., electrode materials in a capacitor structure. Memorydevices may also include thin layers of other materials that serve ascomponents of a storage node, e.g., a top electrode of a capacitorstructure, dielectric material, bottom electrode of the capacitorstructure. A dielectric material may be formed between the two electrodematerials, e.g., top and bottom electrode.

There are thermal or electrical stresses that may occur during afabrication process, particularly after storage node, e.g., capacitor,formation in dynamic random access memory (DRAM) cell back end of theline (BEOL) fabrication processes. To reduce oxygen vacancies caused bythe negative effects of the thermal stressors and/or to increase thebreakdown voltage of a cell, at least one embodiment of the presentdisclosure includes forming a barrier material between electrodes and adielectric layer of a storage node, e.g., capacitor. Forming a barriermaterial between electrodes and the dielectric layer of a capacitor isprovided herein as an illustrative example. However, embodiments of thepresent disclosure are not so limited. For example, embodiments of thebarrier material may be used in other devices such as a NAND high-kblocking oxides, or a high-k Complementary Metal Oxide Semiconductor(CMOS) structures, or any other high-k access device. Embodiments mayalso include forming a plurality of barrier materials in a bi-layerand/or gradient manner between conductive and dielectric layers.

Oxygen vacancies may be created in a cell dielectric layer due tothermal stresses induced during downstream processing or due toelectrical stresses during the actual operation of the device. Thesedefects may lead to worse dielectric leakage, lower dielectric breakdownvoltage and lower device reliability. In order to mitigate this issue,methods for forming a barrier material between electrodes and thedielectric material, are described herein. As an example, a barriermaterial may be deposited on the dielectric material between thedielectric material and the top electrode and/or on the bottom electrodebetween the bottom electrode and the dielectric material. The barriermaterial may also be deposited on both sides of the dielectric material.For example, a first barrier material may be deposited on top of thebottom electrode, below the dielectric material, while a second barriermaterial may be deposited above the dielectric material, below the topelectrode.

Fabrication of semiconductor structures, such as storage nodes of amemory device, may involve moving semiconductor wafers, upon whichsemiconductor structures are being formed, in and out of variousprocessing apparatus. Different structures may be formed “in-situ”,e.g., in place in a processing apparatus, and/or “ex-situ”, e.g.,between various processing apparatus, in a semiconductor fabricationprocess. Various processes may include using multiple semiconductorchambers to perform various semiconductor fabrication processes. Hence,a semiconductor wafer, and semiconductor structures formed thereon, maybe transported between different semiconductor fabrication apparatusesduring a semiconductor fabrication process.

As noted, as a semiconductor fabrication process is performed, adielectric material may go through thermal stress from later back end ofthe line (BEOL) processes which may result in a neighboring electrodescavenging oxygen from the dielectric material. Such effects produceoxygen vacancies in the dielectric material. Oxygen vacancies may leadto a lower dielectric breakdown voltage and higher dielectric leakages.According to embodiments described herein, a barrier material may beused to prevent oxygen vacancy defects within the dielectric material.The barrier material structure and methods described herein may beformed “in-situ” or “ex-situ”.

The present disclosure includes methods, apparatuses, and systemsrelated to forming a barrier material between electrodes and adielectric material, e.g., storage cell in a capacitor. An example of amethod described herein includes forming a dielectric material on abottom electrode material of a storage node in a semiconductorfabrication process. The method further includes forming a barriermaterial on the dielectric material between the dielectric material anda top electrode to reduce oxygen vacancies which may occur throughoxygen scavenging by the top electrode in higher temperature BEOLprocesses, for example. The method further includes forming a topelectrode on the barrier material.

In the following detailed description of the present disclosure,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration how one or more embodimentsof the disclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure. As used herein, “a number of” something mayrefer to one or more such things. For example, a number of capacitorsmay refer to at least one capacitor.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the figure number of the drawing and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, reference numeral104 may reference element “04” in FIG. 1, and a similar element may bereferenced as 204 in FIG. 2. Multiple analogous elements within onefigure may be referenced with a reference numeral followed by a hyphenand another numeral or a letter. For example, 302-1 may referenceelement 302-1 in FIGS. 3 and 302-2 may reference element 302-2, whichmay be analogous to element 302-1. Such analogous elements may begenerally referenced without the hyphen and extra numeral or letter. Forexample, elements 302-1 and 302-2 or other analogous elements may begenerally referenced as 302.

Again, it is noted that while the present disclosure discusses, forexample illustration, a process in reference to a barrier layer betweenan electrode and a dielectric layer of a storage node in the form of acapacitor cell and in the context of a DRAM memory array. However,embodiments are not limited to this example structure, circuitry, ordevice formation in a semiconductor fabrication process. Embodiments maycover forming a barrier material on other semiconductor components, suchas access lines (e.g., wordlines), sense lines (e.g., digit lines, bitlines, etc.), or otherwise conductive surfaces, and devices producedtherefrom, as formed according to the techniques described herein. Forexample, embodiments of the barrier material are not limited to forminga barrier material on a dielectric material in connection with forming aDRAM memory array. Embodiments may be used in forming a barrier materialon a high-k blocking oxide in connection with forming a NAND device orother devices. Similarly, embodiments may be used with forming thebarrier material in a Complementary Metal Oxide Semiconductor (CMOS)high-k fabrication process.

FIG. 1 illustrates an example top-down view of a storage node includinga barrier material formed between the dielectric layer and a topelectrode of a storage node in accordance with a number of embodimentsof the present disclosure. FIG. 1 illustrates storage node 130 as acapacitor 130, including the barrier material 102. However, embodimentsof the present disclosure are not limited to capacitors as storagenodes.

FIG. 1 illustrates a single-sided pillar capacitor 130 in which a bottomelectrode 118 may be formed in contact with a fill material 119.Non-limiting examples of the fill material 119 include polysilicon,silicon nitride, titanium nitride, tungsten, and doped versions thereof.Although not illustrated, embodiments, as described herein, may also beexecuted on other single-sided capacitor types, or a double-sidedcapacitor structure, etc.

The bottom electrode 118 may be formed on the fill material 119 to athickness of a range between 15 to 65 angstroms (Å). However,embodiments are not limited to this example and the bottom electrode 118may be formed from conductive materials and to various widths (e.g.,thicknesses) as suited to a particular design rule for the formation ofan operable capacitor for a semiconductor device. Non-limiting examplesof the bottom electrode 118 may include a platinum (Pt) material, aruthenium (Ru) material, a titanium nitride (TiN) material, a doped TiNmaterial (such as titanium silicon nitride (TiSiN) or titanium boronnitride (TiBN)), a tungsten (W) material, a molybdenum (Mo) material, atantalum nitride (TaN) material, an aluminum (Al) material, a rhodium(Rh) material, a tungsten nitride (WN) material, and a ruthenium oxide(RuO₂) material.

A dielectric material 104 may be formed in contact with the bottomelectrode 118. A non-limiting example of the dielectric material 104 isa zirconium oxide material. The dielectric material 104 may be formedfrom a high dielectric constant (high-k) material. A high-k material mayhave a dielectric constant above 9. Other non-limiting examples of thedielectric material 104 may include aluminium oxide (AlO₃), zirconiumoxide (ZrO₂), hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), amongothers. The dielectric material 104 may be formed on the bottomelectrode 118 to a thickness of a range between 10 to 70 angstroms (Å).Embodiments, however, are not limited to this example thickness rangeand the dielectric material 104 may be formed to various widths (e.g.,thicknesses) as suited to a particular design rule and to achieve thegoals described herein for the formation of an operable capacitor for asemiconductor device.

According to various embodiments, a barrier material 102 is formed incontact with the dielectric material 104 between the dielectric material104 and an electrode, e.g., a top electrode 115. The barrier material102 may be formed on the dielectric material 104 to a thickness of arange between 3 to 20 angstroms (Å). The barrier material 102 may or maynot be formed from conductive materials and may be formed to variouswidths (e.g., thicknesses) as suited to a particular design rule and toachieve the goals described herein for the formation of an operablecapacitor for a semiconductor device. The barrier material 102 may beformed by depositing a high oxygen content TiO_(x)N_(y) film, using anatomic layer deposition (ALD) process. The deposition process mayinclude flowing a titanium tetrachloride (TiCl₄) gas to a surface of thedielectric material 104 in a vacuum reaction chamber of a semiconductorfabrication processing tool followed by flowing purging inert gases.Subsequently, the deposition process may include flowing an ammonia(NH₃) gas into the vacuum reaction chamber of the semiconductorfabrication processing tool and then flowing purging inert gases. Thissequence may be repeated for some number of iterations, e.g., cycles,for a resultant TiN deposition. According to embodiments, the depositionsequence just described is interspersed with a controlled flow of oxygenprecursors as gas reactants into the vacuum reaction chamber of thesemiconductor fabrication processing tool followed by flowing purginginert gases. This sequence may also be repeated for some number ofiterations, e.g., cycles. Non-limiting examples of the oxygen reactantsmay include ozone (O₃), water (H₂O), nitrous oxide (N₂O), nitric oxide(NO), H₂/O₂ plasma, among other oxygen precursors.

The oxygen content of the TiO_(x)N_(y) film may be tailored by adjustingthe number of cycles conducted of the TiN deposition relative to thenumber of cycles conducted flowing the oxygen precursors during the ALDprocess. The relative number of cycles is referred to herein as theTiN:O₂ cycle ratio. By way of example only, the oxygen content in theTiO_(x)N_(y) film may be tailored by adjusting the number of cycles ofTiN deposition relative to the number of cycles of oxygen deposition. Byincreasing the number of cycles of the oxygen deposition relative to thenumber of cycles of the TiN deposition, the oxygen content in the TiNmay be increased. Similarly, by decreasing the number of cycles of theoxygen deposition relative to the number of cycles of the TiNdeposition, the oxygen content in the TiO_(x)N_(y) film may bedecreased. By way of example only, conducting a 10:1 TiN:O₂ cycle ratioproduces a TiO_(x)N_(y) film having a higher oxygen content than thatachieved using a 40:1 TiN:O₂ cycle ratio. In some embodiments, by way ofexample and not by way of limitation, the oxygen content in theTiO_(x)N_(y) film may be controlled, by a TiN:O₂ cycle ratio in a rangeof between 1 to 50. Embodiments, however, are not limited to thisexample.

Other examples of titanium precursors may also include, but are notlimited to, tetrakis (ethylmethylamido) titanium (TEMAT), tetrakis(dimethylamido) titanium (TDMAT), titanocenes or combinations thereof.Other examples of nitrogen precursors may also include, but are notlimited to, nitrogen (N₂), ammonium (NH₄+), or combinations thereof.Atomic layer deposition (ALD), single wafer tools, batch furnace tools,chemical vapor deposition (CVD), or any variant of ALD or depositionschemes, may be used in forming the barrier material 102.

As one continuing example, not to the exclusions of others, oxygen maybe flowed in the above described semiconductor fabrication processes ata flowrate in a range of between 50 to 2000 standard cubic centimetersper minute (sccm) with an oxygen flow time in a range of between 0.2 to600 seconds (s). The resultant barrier material 102, e.g., a resultanttitanium oxynitride (TiO_(x)N_(y)) film, may have an oxygen content inthe range of between 3 to 60 atomic % of the TiO_(x)N_(y) film. In someexample embodiments the TiO_(x)N_(y) film may be deposited in atemperature range of between 350° Celsius (C) to 550° C. The resultinghigh oxygen content of the barrier material 102 may reduce oxygenscavenging from the dielectric material 104 by neighboring electrodes inlater BEOL processing steps.

The resulting barrier material 102, existing as a TiO_(x)N_(y) film, maybe formed by having a titanium nitride (TiN) compound and a titaniumoxide (TiO₂) compound existing together as an artificial layer. Theresulting combination of these compounds may also be referred to hereinas a TiO_(x)N_(y) barrier layer 102.

As shown in FIG. 1, a top electrode 115 may be formed in contact withthe barrier material 102. The top electrode 115 may be formed on thebarrier material 102 to a thickness of a range between 10 to 40angstroms (Å). The top electrode 115 may be formed from conductivematerials and to various widths (e.g., thicknesses) as suited to aparticular design rule for the formation of an operable capacitor for asemiconductor device. Non-limiting examples of the top electrode 115 mayinclude a platinum (Pt) material, a ruthenium (Ru) material, a titaniumnitride (TiN) material, a doped TiN material, a tungsten (W) material, amolybdenum (Mo) material, a tantalum nitride (TaN) material, an aluminum(Al) material, a rhodium (Rh) material, a tungsten nitride (WN)material, and a ruthenium oxide (RuO₂) material.

Fabrication of semiconductor structures may involve moving semiconductorwafers, upon which semiconductor structures are being formed, into andout of fabrication apparatus as part of a particular fabricationprocess. Certain fabrication processes may be performed together,“in-situ”, within a particular fabrication apparatus and controlledenvironment setting, e.g., within a vacuum environment of a particulartool, and other fabrication processes may be performed separately,“ex-situ”, after a wafer has been moved in the fabrication process, orthe control environment settings of a particular tool have changed,according to various semiconductor fabrication techniques. Hence, thesemiconductor structure may be transported between differentsemiconductor fabrication apparatuses during a semiconductor fabricationprocess. This may include using multiple semiconductor chambers toperform various semiconductor fabrication processes. Accordingly,various process steps associated with the barrier material 102 formationprocess described herein may be performed either “in-situ” or “ex-situ”.

In some embodiments, the barrier material 102 may be formed in a layer“within” the top electrode material 115. Hence, the resultant structuremay have a first layer of a top electrode material 115 below a barriermaterial 102, e.g., the TiOxNy film, between the barrier material 102and the dielectric layer 104. A second layer of the top electrodematerial 115 may then exist above the barrier material 102. In thisexample, the structure shown in FIG. 1 would instead include: a fillmaterial 119, a bottom electrode 118, a dielectric material 104, a firstlayer of the top electrode material 115, then next a barrier material102, and then a second layer of the top electrode material 115 formedupon the barrier material 102.

FIG. 2 illustrates another barrier material 202 placement in an exampletop-down view of a storage node. The example embodiment of FIG. 2illustrates the barrier material 202 formed between a bottom electrode218 and the dielectric layer 204. While FIG. 2 illustrates asingle-sided pillar capacitor 232 structure, embodiments are not solimited. Again, for example, the barrier material 102 placement may beexecuted on a double-sided capacitor. For ease of illustration, thetop-down view 232 may include the same or similar elements as theexample top-down view 130 as referenced in FIG. 1. For example, the fillmaterial 219 may be analogous or similar to fill material 119 describedin connection with FIG. 1. Bottom electrode 218 may be analogous orsimilar to the bottom electrode 118 described in connection with FIG. 1.The barrier material 202 may be analogous or similar to barrier material102 described in detail in connection with FIG. 1. And further, thedielectric material 204 and top electrode 215 may be analogous orsimilar to the dielectric material 104 and the top electrode 115described in connection with FIG. 1.

In this embodiment, the timing and fabrication process may be changed toform the barrier material 202 between the bottom electrode 218 and thedielectric material 204. The bottom electrode may be formed in contactwith a fill material 219 and the barrier material 202 is formed, asdescribed herein, is formed in contact with the bottom electrode 218,between the bottom electrode 218 and a dielectric material 204. In thisexample, the dielectric material 204 is thus formed in direct contact tothe top electrode 215.

FIG. 3 illustrates another barrier material, 302-1 and 302-2, placementin an example top-down view of a storage node. The example of FIG. 3illustrates the barrier material 302-1 being formed between the topelectrode 315 and the dielectric material 304 as well as the barriermaterial 302-2 being formed between the bottom electrode 318 and thedielectric material 304. In some embodiments the barrier materials 302-1and 302-2 may be the same thickness, and/or composition, and/or beformed according to a same process technique among those describedherein. Or, alternatively, the barrier materials 302-1 and 302-2 may beof different thicknesses, and/or composition, and/or be formed accordingto different process techniques among those described herein. Again,while FIG. 3 illustrates a single-sided pillar capacitor 334,embodiments are not so limited. For example, embodiments, describedherein, may be implemented on a double-sided capacitor, or othergeometry.

In the example embodiment of FIG. 3, the top down 334 may include thesame or similar elements as the example top-down views 130 and 232 asreferenced in FIGS. 1 and 2, respectively. For example, the fillmaterial 319 may be analogous or similar to fill material 119 and 219 ofFIGS. 1 and 2, respectively. The bottom electrode 318 may be analogousor similar to bottom electrode 118 and 218 of FIGS. 1 and 2,respectively. The dielectric material 304 may be analogous or similar todielectric material 104 and 204 of FIGS. 1 and 2, respectively. And, thetop electrode 315 may be analogous or similar to top electrode 115 and215 of FIGS. 1 and 2, respectively.

In this embodiment, a bottom electrode 318 may be formed in contact witha fill material 319 and an “inner” barrier material 302-2. The innerbarrier material 302-2 may be formed between, and in contact with, thebottom electrode 318 and a dielectric material 304. The dielectricmaterial 304 may be formed in contact with “both” the inner barriermaterial 302-2 and an outer barrier material 302-1. The outer barriermaterial 302-1 may be formed between, and in contact with, thedielectric material 304 and a top electrode 315. Thus, the top electrode315 is also formed in contact with a barrier material, e.g., the outerbarrier material 302-1.

In some embodiments, by way of example and not by way of limitation, theinner barrier material 302-2 may be formed to a thickness in a range ofbetween 3 to 20 angstroms (Å). Similarly, the outer barrier material302-1 may be formed to a thickness in a range of between 3 to 20angstroms (Å). Embodiments, however, are not limited to these examples.The barrier material (collectively referred to as 302) may be formed tovarious widths (e.g., thicknesses) as suited to a particular design rulefor the formation of an operable capacitor for a semiconductor device.

FIGS. 1-3 provide examples of the capacitor structures 130, 232, and 334having circular cross-sections. However, embodiments of the presentdisclosure are not so limited. Capacitors 130, 232, and 334 could havesquare, rectangular, or other polygonal cross-sections and geometries.The capacitors 130, 232, and 334 may serve as a storage node of a memorycell, e.g., a DRAM cell. For example, a memory device may include anarray of DRAM memory cells including capacitors 130, 232, and/or 334having barrier materials 102, 202, and 302 formed according toembodiments described herein.

FIG. 4A illustrates an example cross-sectional side view of the storagenode 130 illustrated in FIG. 1 taken along cut line 2-2. Conversely,FIG. 1 illustrates a cross-sectional view of the capacitor 431 along thecut line 1-1 illustrated in FIG. 4A. The component arrangement ofcapacitor 431 is thus analogous to that of capacitor 130 illustrated inFIG. 1. The numbered elements in FIG. 4A are analogous to the numberedelements shown in FIG. 1. For example, the fill material 419 isanalogous or similar to fill material 119 of FIG. 1. The bottomelectrode 418 is analogous or similar to bottom electrode 118 of FIG. 1.The dielectric material 404 is analogous or similar to second nitridematerial 104 of FIG. 1. The barrier material 402 is analogous or similarto barrier material 102 of FIG. 1. And, the top electrode 415 isanalogous or similar to top electrode 115 of FIG. 1.

However, it is noted that in the cross-sectional view 431 of FIG. 4A,the numbered elements could have an alternative arrangement analogous tothe various barrier material placement alternative shown among theexample cross-sectional, top-down views 130, 232, and 334 referenced inFIGS. 1, 2, and 3, respectively.

As illustrated in FIG. 4A, the capacitor 431 may include the bottomelectrode 418 which may be formed in contact with a fill material 419.For example, the fill material 419 may be formed within a cavity formedby the bottom electrode 418. The bottom electrode 418 may be formed incontact with the fill material 419 and in contact with a dielectricmaterial 404. For ease of illustration only, the bottom electrode 418 isfurther illustrated on a working surface of a semiconductor material401, which according to one semiconductor fabrication process may beprocessed to become a conductive contact from an access device to thebottom electrode 418 of capacitor 431. The dielectric material 404 maybe formed in contact with the bottom electrode 418 and a barriermaterial 402. The barrier material 402 may be formed between, and incontact, with the dielectric material 404 and a top electrode material415.

As noted above, forming the barrier material 402 between the topelectrode 415 and the dielectric material 404 may reduce oxygenscavenging from the dielectric material 404 by the top electrode 415during subsequent processing steps and reduce oxygen vacancies withinthe dielectric material 404. The reduction of oxygen vacancies mayimprove the dielectric breakdown voltage and reduce the dielectricmaterial 404 leakage. The barrier material 402 may increase an effectivework function in a range of between 0.0 to 0.5 eV.

FIG. 4B illustrates another barrier material formation and placementembodiment in an example cross-sectional side view of a storage node.The example cross-sectional, side view of FIG. 4B illustrates a“bi-layer” embodiment of the barrier material having layers 402-1 and402-2 formed between a top electrode 415 and a dielectric layer 404 of astorage node, e.g., capacitor 435. The capacitor 435 and componentsthereof may be analogous to capacitors 130, 232, 334, and 431 andcomponents thereof illustrated in FIGS. 1, 2, 3, and 4A. Hence, thecross-sectional view 435 may include the same or similar elements as theexample top-down views 130, 232, 334, and cross-sectional view 431 asreferenced in FIGS. 1, 2, 3, and 4A respectively. For example, the fillmaterial 419 may be analogous or similar to fill material 119, 219, and319 of FIGS. 1, 2, and 3, respectively. The bottom electrode 418 may beanalogous or similar to bottom electrode 118, 218, and 318 of FIGS. 1,2, and 3, respectively. The dielectric material 404 may be analogous orsimilar to dielectric material 104, 204, and 304 of FIGS. 1, 2, and 3,respectively. The top electrode 415 may be analogous or similar to topelectrode 115, 215, and 315 of FIGS. 1, 2, and 3, respectively. However,the particular difference illustrated in FIG. 4B is that the barriermaterial has a “bi-layer” composition having distinct layers 402-1 and402-2. Again, for ease of illustration only, the bottom electrode 418 isillustrated on a working surface of a semiconductor material 401 whichaccording to one semiconductor fabrication process may be processed tobecome a conductive contact to the bottom electrode 418.

In some embodiments, as illustrated in FIGS. 1, 2, 3, and 4A the barriermaterial may be substantially one, homogenous layer with a substantiallyfixed, continuous, or relatively evenly distributed oxygen contentthroughout the barrier material. Alternatively, the barrier materialshown in FIGS. 1, 2, 3, and 4A may have a gradient in oxygen content inthe TiOxNy film, gradually decreasing or increasing in oxygen contentthroughout the barrier material along one direction or another. As notedabove, the oxygen content of the TiO_(x)N_(y) film may be tailored byadjusting the number of cycles conducted of the TiN deposition relativeto the number of cycles conducted flowing the oxygen precursors duringthe ALD process. Thus, by increasing the number of cycles of the oxygendeposition relative to the number of cycles of the TiN deposition, theoxygen content in the TiO_(x)N_(y) film may be increased. Similarly, bydecreasing the number of cycles of the oxygen deposition relative to thenumber of cycles of the TiN deposition, the oxygen content in theTiO_(x)N_(y) film may be decreased. Accordingly, the barrier materialformation may be controlled to have a gradient composition in oxygencontent throughout the barrier material.

However, as shown in FIG. 4B, in some example embodiments the barriermaterial may comprise of two (2), or more, distinct layers, e.g., 402-1and 402-2. In some example embodiments, a “first” layer of the barriermaterial 402-1, e.g., a “bottom” layer, shown in the example of FIG. 4Bmay be formed in contact with the dielectric material 404. For example,the first layer 402-1 may be formed according to processing techniquesdescribed herein to “purposefully” achieve a higher oxygen content,e.g., higher oxygen content in a first layer of TiO_(x)N_(y) film, in alayer closest to the dielectric material 404. As noted above, the oxygencontent of the TiO_(x)N_(y) film may be tailored by adjusting the numberof cycles conducted of the TiN deposition relative to the number ofcycles conducted of the oxygen deposition during the ALD process. Hence,the bi-layer 402-1 and 402-2 barrier material may be formed to have oneor more, e.g., multiple, distinct portions. A “second” layer of thebarrier material 402-2, e.g., a “top” layer, shown in the example ofFIG. 4B may be formed in contact with the top electrode material 415. Inthis example, the second layer 402-2 may be formed according toprocessing techniques described herein to purposefully achieve a loweroxygen content, e.g., lower oxygen content in a second layer ofTiO_(x)N_(y) film, than that of the first layer of the barrier material402-1, or than that of a preceding barrier material layer in amulti-layer barrier material composition having more that two (2)distinct layers.

Again, FIGS. 1-4B are example embodiments of geometries of capacitorswith barrier materials formed according to the techniques describedherein between dielectric layer, e.g., 104 in FIG. 1, and electrodes,e.g., top electrode 115 in FIG. 1. The example illustrations show thecapacitors 130, 232, 334, 431, and 435 having a bottom electrodesurrounding the fill material and separated from the top electrode by adielectric material. However, embodiments of the present disclosure arenot so limited. Other embodiment configurations may equally benefit froma barrier material separating a dielectric from an electrode. Forexample, alternate capacitors geometries may include “inside-out”designs such that the fill material may be surrounded by the topelectrode which may surrounded by the barrier material which may besurrounded by a dielectric material which may be surrounded by thebottom electrode. Embodiments are not so limited to these examples.

FIG. 5 is a flow diagram of an example method 550 for forming a barriermaterial between an electrode and a dielectric material. In the exampleof FIG. 5, a barrier material is formed between a dielectric and a topelectrode of a storage node in a semiconductor fabrication process. Atblock 552, the method 550 may include forming a dielectric material on abottom electrode material of a storage node in a semiconductorfabrication process. In this embodiment, a storage node may be acapacitor.

The bottom electrode may be formed to a thickness of a range between 15to 65 angstroms (Å). Non-limiting examples of the bottom electrode mayinclude a platinum (Pt) material, a ruthenium (Ru) material, a titaniumnitride (TiN) material, a doped TiN material, a tungsten (W) material, amolybdenum (Mo) material, a tantalum nitride (TaN) material, an aluminum(Al) material, a rhodium (Rh) material, a tungsten nitride (WN)material, and a ruthenium oxide (RuO₂) material. A fill material may bedeposited within the geometry of the bottom electrode.

A dielectric material may be formed over and in contact with the bottomelectrode. A non-limiting example of the dielectric material is azirconium oxide material. The dielectric material may be formed from ahigh dielectric constant (high-k) material. A high-k material may have adielectric constant above 9. Other non-limiting examples of the bottomelectrode may include aluminium oxide (Al₂O₃), zirconium oxide (ZrO₂),hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), among others. Thedielectric material may be formed on the bottom electrode to a thicknessof a range between 10 to 70 angstroms (Å). Embodiments are not limitedto these example materials or thickness for the dielectric material.

At block 554, the method 550 may include forming a barrier material onthe dielectric material to reduce oxygen vacancy formation in thedielectric layer. Oxygen vacancies may be created in the dielectricmaterial, e.g., cell, due to thermal stresses induced during downstreamprocessing or due to electrical stresses during the actual operation ofthe device. These defects may lead to worse dielectric material leakage.In prior approaches, titanium nitride (TiN) top electrodes may have beendeposited on the dielectric, but the TiN top electrodes alone did notmitigate the effects of these stresses. According to embodimentsdescribed herein, however, a high oxygen content barrier material, e.g.,a TiO_(x)N_(y) film, may be formed between the dielectric and anadjacent electrode to mitigate the formation of oxygen vacancies,improve dielectric breakdown voltage, and better reduce dielectricleakage.

The barrier material is formed in contact with the dielectric materialand between the dielectric material and a top electrode. The barriermaterial may be formed on the dielectric material to a thickness of arange between 3 to 20 angstroms (Å). Embodiments, however, are notlimited to this example thickness range. According some embodiments, thebarrier material may be formed by depositing a high oxygen contentTiO_(x)N_(y) film according to an ALD process as described herein.

As one example, the deposition process may include flowing a titaniumtetrachloride (TiCl₄) gas to a surface of the dielectric material 104 ina vacuum reaction chamber of a semiconductor fabrication processing toolfollowed by a purge of the unreacted inert gases. Subsequently, thedeposition process may include flowing an ammonia (NH₃) gas into thevacuum reaction chamber of the semiconductor fabrication processing tooland flowing purging inert gases to produce a resultant TiN deposition.This sequence may be repeated for some number of iterations, e.g.,cycles. According to embodiments, the deposition sequence just describedis interspersed with a controlled flow of oxygen gas reactants into thevacuum reaction chamber of the semiconductor fabrication processing toolfollowed flowing purging inert gases for some number of cycles to form ahigh oxygen content TiOxNy film (barrier material 102) on a surface ofthe dielectric material 104. Non-limiting examples of the oxygenreactants may include ozone (O₃), water (H₂O), nitrous oxide (N₂O),nitric oxide (NO), H₂/O₂ plasma, among other oxygen precursors.Iterations of the above described titanium tetrachloride (TiCl₄) andammonia (NH₃) gas sequence followed by oxygen reactant flow may berepeated through some number of alternating iterations, e.g., cycles.The oxygen content of the TiO_(x)N_(y) film may be tailored by adjustingthe number of cycles conducted of the TiN deposition relative to thenumber of cycles conducted flowing the oxygen precursors during the ALDprocess. The TiO_(x)N_(y) film (barrier material 102) thickness on asurface of the dielectric material 104 can be controlled by the totalnumber of alternating iterations of the above cycles. The relativenumber of cycles is referred to herein as the TiN:O₂ cycle ratio. Insome embodiments, by way of example and not by way of limitation, theTiN:O₂ cycle ratio is in a range of between one (1) to fifty (50). Theoxygen flow time is in a range of between of 0.2 to 600 seconds and theoxygen flow rate is in a range of between 50 to 2000 standard cubiccentimeters per minute (sccm). Embodiments, however, are not limited tothese example ranges. Other examples of titanium precursors may alsoinclude, but are not limited to, tetrakis (ethylmethylamido) titanium(TEMAT), tetrakis (dimethylamido) titanium (TDMAT), titanocenes orcombinations thereof. Other examples of nitrogen precursors may alsoinclude, but are not limited to, Nitrogen (N₂), Ammonium (NH₄+), orcombinations thereof. Atomic layer deposition (ALD), single wafer tools,batch furnace tools, chemical vapor deposition (CVD), or any variant ofALD or deposition schemes, may be used in forming the barrier material102.

The resultant barrier material, e.g., a resultant titanium oxynitride(TiO_(x)N_(y)) film, may have an oxygen content in the range of between3 to 60 atomic % of the TiO_(x)N_(y) film. The titanium oxynitride(TiO_(x)N_(y)) film may be deposited at a temperature range of between350° Celsius (C) to 550° C. The high oxygen content of the barriermaterial may reduce oxygen scavenging from the dielectric material.Hence, the TiO_(x)N_(y) may be formed by having a titanium nitride (TiN)compound and a titanium oxide (TiO₂) compound existing together as anartificial layer. The combination of these compounds may be referred toas TiO_(x)N_(y) and as such form the barrier material described herein.

Fabrication of semiconductor structures may involve moving semiconductorwafers, upon which semiconductor structures are being formed, in, i.e.,“in-situ”, and out of, “ex-situ”, a vacuum environment according to aparticular semiconductor fabrication process. That is, the semiconductorstructure may be transported between different semiconductor fabricationapparatuses during a semiconductor fabrication process. This may includeusing multiple semiconductor chambers to perform various semiconductorfabrication processes. The barrier material may be deposited “in-situ”or “ex-situ” to other process steps in the storage node formation.

At block 556, the method 550 may include forming a top electrode on thebarrier material. The top electrode may be formed in direct contact withthe barrier material. The top electrode may be formed on the barriermaterial to a thickness of a range between 10 to 40 angstroms (Å).Non-limiting examples of the top electrode may include a platinum (Pt)material, a ruthenium (Ru) material, a titanium nitride (TiN) material,a doped TiN material, a tungsten (W) material, a molybdenum (Mo)material, a tantalum nitride (TaN) material, an aluminum (Al) material,a rhodium (Rh) material, a tungsten nitride (WN) material, and aruthenium oxide (RuO₂) material.

FIG. 6 is another flow diagram of an example method 630 for depositing abarrier material. In the example of FIG. 6, the barrier material isformed between a bottom electrode and a dielectric material of a storagenode in a semiconductor fabrication process. The barrier material may beformed on the bottom electrode according to the methods describedherein. At block 632, the method 630 may include depositing a barriermaterial on a bottom electrode material of a storage node in asemiconductor fabrication process. In some embodiments, a storage nodemay be a capacitor and the bottom electrode may be deposited on the fillmaterial to a thickness of a range between 15 to 65 angstroms (Å).

At block 634, the method 630 may include depositing a dielectricmaterial on the barrier material. The barrier material may have athickness in a range of between 3 to 20 angstroms (Å). The barriermaterial may be formed by depositing high oxygen content titaniumoxynitride (TiO_(x)N_(y)) film using an atomic layer deposition (ALD) asdescribed herein.

A dielectric material may be formed separated from the bottom electrodeby the barrier material. The dielectric material may be formed from ahigh dielectric constant (high-k) material. A high-k material may have adielectric constant above 9. Non-limiting examples of the bottomelectrode may include aluminium oxide (AlO₃), zirconium oxide (ZrO₂),hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), among others. Thedielectric material may be deposited on the bottom electrode to athickness of a range between 10 to 70 angstroms (Å).

At block 636, the method 630 may include depositing a top electrode onthe dielectric material. The top electrode may be deposited on thebarrier material to a thickness of a range between 10 to 40 angstroms(Å). Non-limiting examples of the top electrode may include a platinum(Pt) material, a ruthenium (Ru) material, a titanium nitride (TiN)material, a doped TiN material, a tungsten (W) material, a molybdenum(Mo) material, a tantalum nitride (TaN) material, an aluminum (Al)material, a rhodium (Rh) material, a tungsten nitride (WN) material, anda ruthenium oxide (RuO₂) material.

FIG. 7 is another flow diagram of an example method 780 for forming abarrier material between electrodes and a dielectric material of astorage node in a semiconductor fabrication process. In this exampleembodiment, a barrier material separates both a bottom electrode and atop electrode from the dielectric material. In this embodiment, astorage node may be a capacitor.

In a semiconductor fabrication process a bottom electrode may beconstructed according to various semiconductor fabrication techniques.At block 782, the method 780 may include forming a first barriermaterial on the bottom electrode material. The barrier material may beformed according to the techniques described above and herein. In someembodiments, the first barrier material may be formed between the bottomelectrode and the dielectric material to a thickness of a range between3 to 20 angstroms (Å).

At block 784, the method 780 may include forming a dielectric materialon the first barrier material. The dielectric material may be formedfrom a high dielectric constant (high-k) material. Non-limiting examplesof the bottom electrode may include aluminium oxide (AlO₃), zirconiumoxide (ZrO₂), hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), amongothers. The dielectric material may be deposited on the barrier materialto a thickness of a range between 10 to 70 angstroms (Å).

At block 786, the method 780 may include forming a second barriermaterial on the dielectric material. Again, the barrier material may beformed according to the techniques described above and herein. In thisembodiment, the second barrier material may be formed between thedielectric material and a top electrode to a thickness in a range ofbetween 3 to 20 angstroms (Å). The second barrier material may be formedby depositing a high oxygen content TiO_(x)N_(y) film using an atomiclayer deposition (ALD).

At block 788, the method 780 may include forming a top electrode on thesecond barrier material. The top electrode may be formed on the secondbarrier material to a thickness in a range of between 10 to 40 angstroms(Å). Non-limiting examples of the top electrode may include a platinum(Pt) material, a ruthenium (Ru) material, a titanium nitride (TiN)material, a doped TiN material, a tungsten (W) material, a molybdenum(Mo) material, a tantalum nitride (TaN) material, an aluminum (Al)material, a rhodium (Rh) material, a tungsten nitride (WN) material, anda ruthenium oxide (RuO₂) material.

Forming the first barrier material and the second barrier materialbetween the dielectric and both the top electrode and the bottomelectrode may reduce the oxygen scavenging from the dielectric materialby the electrodes, thus reducing oxygen vacancies within the dielectricmaterial. The reduction of oxygen vacancies may increase the dielectricbreakdown voltage and reduce the dielectric material leakage. Thebarrier material may also increase the effective work function in arange of between 0.0 to 0.5 eV.

FIG. 8 is a functional block diagram of an apparatus 840 forimplementation of an example semiconductor fabrication process inaccordance with a number of embodiments of the present disclosure. Thesystem 840 may include a processing apparatus 841 (e.g., a semiconductorfabrication apparatus). The processing apparatus 841 may be configuredto enable in-situ formation of a barrier material formed betweenelectrodes.

The processing apparatus 841 may include a semiconductor processingchamber 842 to enclose components configured to form, in-situ in asemiconductor processing chamber 842, a barrier material (e.g., thebarrier material 102, 202, 302-1, 302-2, and 402 described inassociation with FIGS. 1-4B) between a top electrode (e.g., the topelectrode 115, 215, 315, and 415 described in association with FIGS.1-4B) and a bottom electrode (e.g., the bottom electrode 118, 218, 318,and 418 described in association with FIGS. 1-4B). The semiconductorprocessing chamber 842 may further enclose a carrier 843 to hold asingle and/or batch semiconductor wafers 844 forming semiconductorstructures such as a top electrode, dielectric material, bottomelectrode, and barrier material between one of both of the electrodesand the dielectric material. The processing apparatus 841 may includeand/or be associated with tools including, for example, a pump unit 845and a purge unit 846 configured to introduce and remove precursors aspart of an atomic layer deposition (ALD) process, or other semiconductorfabrication process, as described herein to form a barrier materialformed between a dielectric material and electrodes. In at least oneembodiment, the processing apparatus 841 may include and/or beassociated with tools including, for example, a pump unit 845 and apurge unit 846 configured to introduce and remove precursors asdescribed herein to form barrier material formed between electrodes. Theprocessing apparatus 841 may further include a temperature control unit847 configured to maintain the semiconductor processing chamber 842 atan appropriate temperature as described herein (e.g., betweenapproximately 350° C. and approximately 550° C.).

The system 840 may further include a controller 848. The controller 848may include, or be associated with, circuitry and/or programming forimplementation of, for instance, in-situ formation of a barrier materialformed between electrodes. Adjustment of such deposition and purgingoperations by the controller 848 may control the thickness of thebarrier material and/or position of the barrier material formed betweenelectrodes as described herein.

The controller 848 can, in a number of embodiments, be configured to usehardware as control circuitry. Such control circuitry can, for example,be an application specific integrated circuit (ASIC) with logic tocontrol fabrication steps, via associated deposition and purgeprocesses, for in-situ formation of a barrier material formed betweenelectrodes.

FIG. 9 is a functional block diagram of a computing system 960 includingat least one memory array having a structure formed in accordance with anumber of embodiments of the present disclosure. In the exampleillustrated in FIG. 9, the system 964 includes a memory interface 966, anumber of memory devices 970-1, . . . , 970-N, and a controller 968selectably coupled to the memory interface 966 and memory devices 970-1,. . . , 970-N. The system 964 may be, for example, a solid-state drive(SSD). The memory interface 966 may be used to communicate informationbetween the system 960 and another device, such as a host 962. The host962 may include a processor (not shown). As used herein, “a processor”may be a number of processors, such as a parallel processing system, anumber of coprocessors, etc. Example hosts may include, or byimplemented in, laptop computers, personal computers, digital cameras,digital recording devices and playback devices, mobile telephones, PDAs,memory card readers, interface hubs, and the like. In a number ofexamples, the host 962 may be associated with (e.g., include or becoupled to) a host interface 963. The host interface 963 may enableexchange of data and commands with a memory interface 966 to a memorydevice 964.

The memory interface 966 may be in the form of a standardized physicalinterface. For example, when the system 964 is used for information(e.g., data) storage in computing system 960, the memory interface 966may be a serial advanced technology attachment (SATA) interface, aperipheral component interconnect express (PCIe) interface, or auniversal serial bus (USB) interface, among other physical connectorsand/or interfaces. In general, however, the memory interface 966 mayprovide an interface for passing control, address, information, scaledpreferences, and/or other signals between a controller 968 of the system964 and the host 962 (e.g., via host interface 963).

The controller 968 may include, for example, firmware and/or controlcircuitry (e.g., hardware). The controller 968 may be operably coupledto and/or included on the same physical device (e.g., a die) as one ormore of the memory devices 970-1, . . . , 970-N. For example, thecontroller 968 may be, or may include, an ASIC as hardware operablycoupled to circuitry (e.g., a printed circuit board) including thememory interface 966 and the memory devices 970-1, . . . , 970-N.Alternatively, the controller 968 may be included on a separate physicaldevice that is communicatively coupled to the physical device (e.g., thedie) that includes one or more of the memory devices 970-1, . . . ,970-N.

The controller 968 may communicate with the memory devices 970-1, . . ., 970-N to direct operations to sense (e.g., read), program (e.g.,write), and/or erase information, among other functions and/oroperations for management of memory cells. The controller 968 may havecircuitry that may include a number of integrated circuits and/ordiscrete components which may include a barrier material formed betweena dielectric material and a conductor according to embodiments describedherein. In a number of examples, the circuitry in controller 968 mayinclude control circuitry for controlling access across the memorydevices 970-1, . . . , 970-N and/or circuitry for providing atranslation layer between the host 962 and the system 964.

The memory devices 970-1, . . . , 970-N may include, for example, anumber of memory arrays 967 (e.g., arrays of volatile and/ornon-volatile memory cells). For instance, the memory devices 970-1, . .. , 970-N may include arrays of memory cells that include structuresdescribed in connection with FIGS. 1-4B. For example, the memory cellsin the memory array 967 of the memory devices 970-1, . . . , 970-N maybe in a RAM architecture (e.g., DRAM, SRAM, SDRAM, FeRAM, MRAM, ReRAM,etc.), a flash architecture (e.g., NAND, NOR, etc.), a three-dimensional(3D) RAM and/or flash memory cell architecture, or some other memoryarray architecture including a barrier material formed between anelectrode and a dielectric material as described herein.

The memory devices 970-1, . . . , 970-N may be formed on the same die. Amemory device (e.g., the memory device 970-1) may include one or more ofarrays of memory cells 967 formed on a die. The memory device 970-1 mayinclude sense circuitry 965 and control circuitry 961 associated withone or more memory arrays 967 formed on the die, or portions thereof.For example, the sense circuitry 965 may be utilized to determine(sense) a particular data value (e.g., 0 or 1) that is stored at aparticular memory cell in a row of an array 967. The control circuitry961 may be utilized to direct the sense circuitry 965 to senseparticular data values, in addition to directing storage, erasure, etc.,of data values in response to a command from the host 962 and/or thehost interface 963. The command may be sent directly to the controlcircuitry 961 via the memory interface 966 or to the control circuitry961 via the controller 968.

The example illustrated in FIG. 9 may include additional circuitry thatis not illustrated so as not to obscure examples of the presentdisclosure. For example, the memory devices 970-1, . . . , 970-N mayinclude address circuitry to latch address signals provided over I/Oconnectors through I/O circuitry. Address signals may be received anddecoded by a row decoder and a column decoder to access the memory array967. It will be appreciated that the number of address input connectorsmay depend on the density and/or architecture of the memory devices970-1, . . . , 970-N and/or the memory arrays 967.

In the above detailed description of the present disclosure, referenceis made to the accompanying drawings that form a part hereof, and inwhich is shown by way of illustration how one or more embodiments of thedisclosure may be practiced. These embodiments are described insufficient detail to enable those of ordinary skill in the art topractice the embodiments of this disclosure, and it is to be understoodthat other embodiments may be utilized and that process, electrical,and/or structural changes may be made without departing from the scopeof the present disclosure.

It is to be understood that the terminology used herein is for thepurpose of describing particular embodiments only and is not intended tobe limiting. As used herein, the singular forms “a”, “an”, and “the”include singular and plural referents, unless the context clearlydictates otherwise, as do “a number of”, “at least one”, and “one ormore” (e.g., a number of memory arrays may refer to one or more memoryarrays), whereas a “plurality of” is intended to refer to more than oneof such things. Furthermore, the words “can” and “may” are usedthroughout this application in a permissive sense (i.e., having thepotential to, being able to), not in a mandatory sense (i.e., must). Theterm “include,” and derivations thereof, means “including, but notlimited to”. The terms “coupled” and “coupling” mean to be directly orindirectly connected physically and, unless stated otherwise, mayinclude a wireless connection for access to and/or for movement(transmission) of instructions (e.g., control signals, address signals,etc.) and data, as appropriate to the context.

While example embodiments including various combinations andconfigurations of semiconductor materials, underlying materials,structural materials, dielectric materials, capacitor materials,substrate materials, silicate materials, nitride materials, buffermaterials, etch chemistries, etch processes, solvents, memory devices,memory cells, sidewalls of openings and/or trenches, among othermaterials and/or components related to determining overlay of featuresof a memory array, have been illustrated and described herein,embodiments of the present disclosure are not limited to thosecombinations explicitly recited herein. Other combinations andconfigurations of the semiconductor materials, underlying materials,structural materials, dielectric materials, capacitor materials,substrate materials, silicate materials, nitride materials, buffermaterials, etch chemistries, etch processes, solvents, memory devices,memory cells, sidewalls of openings and/or trenches related todetermining overlay of features of a memory array than those disclosedherein are expressly included within the scope of this disclosure.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results may be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of one or more embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the one or moreembodiments of the present disclosure includes other applications inwhich the above structures and processes are used. Therefore, the scopeof one or more embodiments of the present disclosure should bedetermined with reference to the appended claims, along with the fullrange of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are groupedtogether in a single embodiment for the purpose of streamlining thedisclosure. This method of disclosure is not to be interpreted asreflecting an intention that the disclosed embodiments of the presentdisclosure have to use more features than are expressly recited in eachclaim. Rather, as the following claims reflect, inventive subject matterlies in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment.

1.-20. (canceled)
 21. An apparatus, comprising: a bottom electrodematerial of a storage node; a first titanium oxynitride (TiO_(x)N_(y))barrier material formed on the bottom electrode material, wherein thefirst barrier material has a first oxygen content; a dielectric materialformed on the first TiO_(x)N_(y) barrier material; a second TiO_(x)N_(y)barrier material, having a second oxygen content which is lower than thefirst oxygen content and formed on the dielectric material to increasean effective work function in a range of between 0.0 eV and 0.5 eV. 22.The apparatus of claim 21, further comprising a top electrode in contactwith the second TiO_(x)N_(y) barrier material.
 23. The apparatus ofclaim 21, wherein the first TiO_(x)N_(y) barrier material and the secondTiO_(x)N_(y) barrier material are formed at a temperature in a range ofbetween 350° to 550° Celsius (C).
 24. The apparatus of claim 21, whereinthe first TiO_(x)N_(y) barrier material and the second TiO_(x)N_(y)barrier material have a thickness in a range of between 3 to 20angstroms (Å).
 25. The apparatus of claim 21, wherein the first TiOxNybarrier material and the second TiOxNy barrier material are formed froma film material.
 26. The apparatus of claim 21, wherein the topelectrode has a thickness in a range of between 10 angstroms to 40angstroms.
 27. The apparatus of claim 21, wherein the first TiO_(x)N_(y)barrier material and the second TiO_(x)N_(y) barrier material are formedon a single-sided pillar capacitor.
 28. The apparatus of claim 21,wherein the first TiO_(x)N_(y) barrier material and the secondTiO_(x)N_(y) barrier material reduces oxygen vacancies in the dielectricmaterial.
 29. An apparatus, comprising: a bottom electrode material of astorage node; a dielectric material formed on the bottom electrodematerial; a multilayer barrier material having an oxygen content in arange of between 3-60 atomic % of the barrier material and formed on thedielectric material, wherein the multilayer barrier material comprises:a first layer having a first oxygen content and formed in contact withthe dielectric material; and a second layer having a second oxygencontent which is lower than the first oxygen content and formed on thefirst layer; and a top electrode formed on the multilayer barriermaterial and in contact with the second layer.
 30. The apparatus ofclaim 29, wherein the multilayer barrier material is a bi-layer barriermaterial comprising the first layer and the second layer.
 31. Theapparatus of claim 29, wherein the multilayer barrier material increasesa breakdown voltage of the dielectric material.
 32. The apparatus ofclaim 29, wherein the apparatus is a single-sided pillar capacitor. 33.The apparatus of claim 29, wherein the apparatus is a double-sidedcapacitor.
 34. The apparatus of claim 29, wherein the first barriermaterial and the second barrier material are formed using a titaniumoxynitride (TiO_(x)N_(y)) material.
 35. The apparatus of claim 34,wherein the oxygen content in the TiOxNy film material is in a range ofbetween 3-60 atomic % of the TiOxNy film.
 36. A method, comprising:forming a dielectric material of a semiconductor structure; and forminga titanium oxynitride (TiO_(x)N_(y)) material on the dielectricmaterial, wherein the TiO_(x)N_(y) material has an oxygen content in arange of between 3-60 atomic % and is formed by: using a titaniumtetrachloride (TiCl4) precursor over the dielectric material; using anammonia (NH3) precursor; using a purging inert gas; repeating iterationsof the TiCl4 precursor and the NH3 precursor; and using an oxygenprecursor in alternating iterations with the TiCl4 precursor and the NH3precursor.
 37. The method of claim 36, further comprising forming theTiOxNy material as a bi-layer material having layers of different oxygencontent.
 38. The method of claim 36, further comprising forming theTiO_(x)N_(y) material with a gradient in oxygen content.
 39. The methodof claim 36, further comprising forming the TiO_(x)N_(y) material with athickness in a range of between 3 to 20 angstroms (Å).
 40. The method ofclaim 36, wherein using the oxygen precursor for a time range of between0 to 600 seconds.